1. Field of the Invention
The present invention generally relates to MOS (Metal Oxide Semiconductor) transistors and semiconductor integrated circuits incorporating the MOS transistors, and more specifically, to MOS transistors provided with a plurality of substantially stripe shaped transistor cells in which each of the plural transistor cells is configured to have an extended gate that is sandwiched between an extended source and an extended drain, and to semiconductor integrated circuits incorporating the MOS transistors.
2. Description of the Related Art
Conventionally, there is known a transistor configuration technique in which plural transistor cells are formed on a semiconductor substrate to form a single MOS (Metal Oxide Semiconductor) transistor. In this case, a transistor cell includes an extended gate electrode (gate), a drain electrode (drain) and a source electrode (source), and the drain and the source are formed to sandwich the gate and are extended in a striped shape approximately parallel to the gate. The source and the drain are alternately arranged in plural transistor cells.
FIGS. 1A through 1C are drawings showing a structure of a related art MOS transistor Tr1. FIG. 1A shows a metal layer M1 capable of applying voltage to the MOS transistor Tr1. FIG. 1B shows a plan view of the structure of the MOS transistor Tr1 formed on a semiconductor substrate WF, and FIG. 1C is a cross sectional view of the structure of the MOS transistor Tr1. Each part of the above structure is correspondingly referenced in the above mentioned figures.
In FIG. 1B, a single transistor cell is formed from an extended gate G1, a drain D and a source S, in which the drain D and the source S are arranged at both sides of the extended gate G1. The number of the formed transistor cells is the same as that of the gate G1, and these transistor cells are arranged to be connected in parallel to form a single MOS transistor Tr1.
Further, two sources S are arranged at both sides of the arranged transistor cells, and back gates BG1 are formed around the perimeter of the arranged transistor cells. Generally, identical electric potential (voltage) is applied to the sources S and the back gates BG1. For an N channel MOS transistor, ground potential is applied to the sources S and the back gates BG1. The electric potential of a power supply is applied to the drains D. Further, through holes H are formed on the drains D, the sources S and the back gates BG1 to allow an electrical connection to the metal layers formed as upper layers.
FIG. 1A shows the structure of a metal layer M1 which applies electric potential to the MOS transistor Tr1. In order to apply the ground potential to the sources S and the back gates BG1, a ground potential supply pattern MG1 is formed to cover the sources S and the back gates BG1. On the other hand, for applying power supply potential to the drains D, a power supply pattern MV1 is formed to cover the drains D. The metal layer M1 applies electric potential to the MOS transistor Tr1 through the through holes H described above.
In FIG. 1C, a cross sectional structure of the MOS transistor Tr1 of FIG. 1B is shown. The sources S and drains D are formed at the surface of the semiconductor substrate WE as N-type diffusion layers which are arranged at the surface at a predetermined interval. Oxide insulating films I are formed on the semiconductor substrate WF located between the N-type diffusion layers, and gates are formed on the oxide insulating films. The semiconductor substrate WF is formed with a P-type layer, while the source S and drain D are formed with N-type diffusion layers. These layers form parasitic NPN type transistors Q1 in the semiconductor substrate WF. A drain D, a source S and a P-type layer of the semiconductor substrate WF respectively correspond to a collector, an emitter and a base of a parasitic transistor Q1. In this case, there is a substrate resistance R1 that is formed between the back gate BG1 having the ground potential and the base of the parasitic transistor Q1. The resistance corresponds to that of the semiconductor substrate WF, and thus the resistance becomes greater by increasing the distance between the base and the end of the back gate BG1 to which ground potential is applied. Therefore, in FIG. 1C, a base resistance R1 of the parasitic transistor Q1 formed at the central part of the semiconductor substrate WF becomes the highest value.
Here, when the base resistance R1 between the base of the parasitic transistor Q1 and the ground becomes greater, the base electric potential tends to become higher. As a result, the parasitic transistor Q1 enters a turned-on state and electric current flows between the emitter and the collector causing a breakdown. That is, a snapback phenomenon can easily occur. Once a snapback phenomenon occurs, an uncontrollable electric current starts flowing between the drain D and source S. In order to prevent this, conventionally, a technique is suggested to increase the gate length of a gate G for improving the breakdown voltage characteristics of a MOS transistor.
FIGS. 2A through 2C are drawings showing a structure of a related art MOS transistor Tr2 which has a longer gate length. FIG. 2A shows a metal layer M2 which applies electric potential to a MOS transistor Tr2, FIG. 28 shows a plan view of a structure of the MOS transistor Tr2 formed on the semiconductor substrate WF, and FIG. 2C is a drawing showing a cross sectional structure of the MOS transistor Tr2. It is indicated that the arrangement of individual parts correspond through the figures. Further, the same reference symbols are used for identical parts of the configuration used in FIG. 1.
In FIG. 2B, each source S and each drain D are arranged at both sides of each gate G2 that is extended in a line shape. The source and drain are arranged to sandwich each gate G2 approximately in parallel to the extended gate G2. Plural transistor cells are formed and two sources S are arranged at both sides of the plural transistor cells. The back gate BG1 surrounds the transistor cells. The basic configuration in which the back gate BG1 is formed around the perimeter of the sources S is similar to FIG. 1B except that the gate G2 has a longer gate length, which is different from FIG. 1B.
FIG. 2C shows a cross sectional view of the MOS transistor TR2 corresponding to the MOS transistor TR2 in FIG. 2B. In this case, there is an NPN-type parasitic transistor Q2 formed of a drain D and source S of N-type diffusion layers, and a P-type layer of the semiconductor substrate WF. A substrate resistance R1 is formed between the base of the parasitic transistor Q2 and a back gate BG1 similar to the case of FIG. 1C. In this case, the breakdown voltage characteristic of the parasitic transistor Q2 is improved because the gate length of the gate G2 has been increased. Thus it becomes more difficult to cause a snapback phenomenon, as compared to the case of FIG. 1C.
FIG. 2A shows a structure of a metal layer M2 formed on an upper layer of the MOS transistor Tr2. The metal layer M2 includes a ground potential supply pattern MG2 and a power potential supply pattern MV2. In FIG. 2A, the ground potential supply pattern MG2 is formed to continuously cover the source S and the back gate BG1 so that the ground potential can be applied to the source S and the back gate BG1. The power potential supply pattern MV2 is formed to cover the drain D so that the power supply potential can be applied to the drain D. These features are similar to the case of FIG. 1A, however, the gate length L of the gate G2 has been increased and the width of the ground potential supply pattern MG2 has been increased to correspond to the increased gate length L. As a result, the fact that the separation of the power potential supply pattern MV2 has been increased is a different point from the case of FIG. 1A.
As described above, conventionally, a desired breakdown voltage characteristic is achieved by increasing the gate length L, in which the gate length L is determined by the required breakdown voltage of a MOS transistor Tr2.
Further, there is a related technique that prevents the transistors of a protection circuit from degradation of the breakdown voltage characteristics. In this case, the semiconductor apparatus includes a transistor formed in a single conducting type well region, in which the conducting regions of a source and drain are opposite to that of the well and the source and drain are formed to sandwich a gate electrode. Also a back gate region with a single conducting type is arranged on the surface of the source region and penetrates the source region to the single conducting type well region. The position of the back gate region at the surface of the source region is arranged to maximize the resistance between a position right below the gate in the well region and the back gate region (for example, Japanese Patent Application Publication No. 10-12824).
However, in the configuration of the related technique described above in FIG. 2, when the gate length L is lengthened without changing the gate width, the gate capacitance increases as the gate area is increased with the gate length. This causes a problem in that the MOS transistor Tr2 can operate at high speed.
Further, when the current driving capability of the MOS transistor Tr2 needs to be constant, the gate width must be widened to prevent the degradation of the current driving capability caused by lengthening the gate length. Thus, the gate area and the device area increase with the gate width, and eventually, the gate capacitance and the parasitic capacitance of the source and drain are increased. As a result, the parasitic capacitance prevents the MOS transistor Tr2 from providing required characteristics, and thus high breakdown voltage characteristics and high speed switching operation cannot be achieved at the same time.
FIG. 3 shows the gate length dependence of snapback voltages and gate capacitances (parasitic capacitances), in which the MOS transistor Tr2 has been manufactured with a related art technique shown in FIG. 2 to improve the breakdown voltage characteristics. In FIG. 3, a chain line indicates a gate capacitance (parasitic, capacitance) characteristic for different gate lengths L and a dashed line indicates snapback voltages for different gate lengths L.
As shown in FIG. 3 with the dashed line, the snapback voltage increases linearly as the gate length L is increased, resulting in the improvement of the breakdown voltage characteristics. However, since the gate parasitic capacitance is drastically increased in a quadratic function manner as indicated by the chain line, it is difficult to increase the breakdown voltage characteristics when providing high speed operations.
It is, therefore, one of the objects of this invention is to provide an improvement of the breakdown voltage characteristics of a MOS transistor capable of operating high speed switching, and to provide semiconductor integrated circuits incorporating the MOS transistor.